Buses

  A bus is a communication path way connecting two or more devices.Take the motherboard and look at the bottom side of it, you can see lines connection to each element. That is a bus.

 System bus
Connects the CPU with main memory and other system components.

 Peripheral device
Device other than the CPU and primary storage.

 Bus clock pluse
Common timing reference for all attached device.

 Data tranfer rate
Rate at which data is transmitted through a medium or communication channel ,as a measurement in data unit per time interval.

 Bus protokol
Set of rule which by data moves between devices.Eg : number of bit,number of address


Bus operation

To send data to another device
    - First the module must get permission to use the bus, and then only can send the data
To request data from another device
   - First the module must get permission to use the bus, and then send a request signal to
      the other device and finally wait for the device to send the data.



Internal/External Buses



System Bus

 Addres Bus : Use to transfer address from PC to memory.
Data Bus     : Carry data,instuction and address between main memory and ALU
Control Bus : Carry signal such as interrupt ,timing and acknowledgment to and  from
                      component.

Single Bis problem

 - Many device may share one single bus for their operation.
- This may lead to Propagation.
- Propagation delay is the time taken for a signal to travel from a point of input to a point of
  output.
- Result will be measured in microsecond,etc
- To solve the problem use multiple busses

Bus Hierarchy
The Processor Bus (System Bus):
This is the highest-level bus that is used to send information to and from the processor.
The Cache Bus:
Higher-level architectures employ a dedicated bus for accessing the system cache.
This is sometimes called a backside bus. 
The Memory Bus:
This is a second-level system bus that connects the memory subsystem to the processor.
In some systems the processor and memory buses are basically the same thing.
The Local I/O Bus:
This is a high-speed input/output bus used for connecting performance-critical peripherals to the memory and processor. For example, video cards, disk storage devices, high-speed networks interfaces generally use a bus of this sort.
The Standard I/O Bus:
Used for slower peripherals (mice, modems, regular sound cards, low-speed networking) and also for compatibility with older devices.


The illustration show how the various busses connect to the CPU

Characteristic of Bus

Every bus is composed of two distint part : Data bus,Address bus and Control bus.

           Data bus : The line that actually carry the data being transfered.
           Address bus : Is the set of line that carry information about where in memory the
                                    data is to be transfered to or from.
          Control bus : Control line that control how the bus functions and allow user of
                                 the bus signal when data is available.

Bus Width : The number of bit that can travel in parallel along the bus.
                       The wider the bus,the better it is since more data can flow at one time.

Bus Speed : How many bits can be sent within a second.
                        How fast the bits are following through the bus.

Bus Bandwidth : Also known as throughtput which refers to the total
                                amount of data that can be transfered on the bus in a given unit of time.
                               Bandwidth = Bus Speed x Bus Width.

Bus perfomance

Transfer time : Amount of time taken for data to be delivered in a single transaction.

Bandwidth : Measures the capacity of the bus.
                     How much can the bus sent at one time.

Bus standard



System board
Input / output Interface
The computer system’s I/O architecture is its interface to the outside world. This architecture is designed to provide a systematic means of controlling interaction with the outside world and to provide the operating system with the information it needs to manage I/O activity effectively.

There are three principal I/O techniques :


Program Input/Output
Input output occurs under the direct and continuous control of the the program  requesting the I/O operation.

Interrupt driven I/O
A program issues an I/O command and then continues to execute,until is interrupted by the I/O hardware to signal the end of the I/O operation.

Direct memory access
Specialized I/O processor take over control of an I/O operation to move a large block data.

Each modul acts as an interface to the system bus or central switch and control one more peripheral device.
Input/Output module help communication betwen the peripheral and the bus.

Peripherals and the System Bus

There are a wide variety of peripherals each with varying methods of operation
  • Impractical to for the processor to accommodate all
    Data transfer rates are often slower than the processor and/or memory.
  • Impractical to use the high-speed system bus to communicate directly
    Data transfer rates may be faster than that of the processor and/or memory.
  • This mismatch may lead to inefficiencies if improperly managed
    Peripheral often use different data formats and word lengths.



    External Devices

    • Human readable     : communicate with the computer user – CRT.
    • Machine readable   : communicate with equipment – disk drive or tape drive.
    • Communication      : communicate with remote devices – may be human readable or
                                              machine readable.




    The External Device – I/O Module
    • Control signals: determine the function that will be performed.
    • Data                     : set of bits to be sent of received.
    • Status signals   : indicate the state of the device.
    • Control logic     : controls the device’s operations.
    • Transducer       : converts data from electrical to other forms of energy.
    • Buffer                 : temporarily holds data being transferred.
    Keyboard/Monitor

    •  Most common means of computer/user interaction.
    •  Keyboard provides input that is transmitted to the computer.
    •  Monitor displays data provided by the computer.
    •  The character is the basic unit of exchange.
    •  Each character is associated with a 7 or 8 bit code.

    Disk Drive
    • Contains electronics for exchanging data, control, and status signals with an I/O
       module.
    • Contains electronics for controlling the disk read/write mechanism.
    • Fixed-head disk – transducer converts between magnetic patterns on the disk
      surface and bits in the buffer.
    • Moving-head disk – must move the disk arm rapidly across the surface.

    I/O Modules

    Module Functions:
    • Control and timing.
    • CPU communication.
    • Device communication.
    • Data buffering.
    • Error detection.

     I/O control and timing steps
    •      Processor checks I/O module for external device status.
    •      I/O module returns status.
    •      If device ready, processor gives I/O module command to request data transfer.
    •      I/O module gets a unit of data from device.
    •      Data transferred from the I/O module to the processor.


    CPU communication
    • Command decoding
    I/O module accepts commands from the processor sent as signal on the
    control bus.
    • Data
    data exchanged between the processor and I/O module over the data bus.
    • Status reporting
    common status signals BUSY and READY are used because peripherals are slow.
    • Address recognition
    I/O module must recognize a unique address for each peripheral that it controls.

    Device communication: commands, status information, and data.

    Data buffering: data comes from main memory in rapid burst and must be buffered by the
                               I/O module and then sent to the device at the device’s rate.

    Error detection: responsible for reporting errors to the processor.

    Input /Output Diagram
    • Module connects to the computer through a set of signal lines – system
      bus.
    • Data transferred to and from the module are buffered with data registers.
    • Status provided through status registers – may also act as control
      registers.
    • Module logic interacts with processor via a set of control signal lines.
    • Processor uses control signal lines to issue commands to the I/O module.
    • Module must recognize and generate addresses for devices it controls.
    • Module contains logic for device interfaces to the devices it controls.
    • I/O module functions allow the processor to view devices is a simple
      minded way.
    • I/O module may hide device details from the processor so the processor
      only functions in terms of simple read and write operations – timing,
      formats,etc.
    • I/O module may leave much of the work of controlling a device visible to
      the processor – rewind a tape, etc…

    I/O channel or I/O processor
    • I/O module that takes on most of the detailed processing burden.
    • Used on mainframe computers.

    I/O controller of device controller
    • Primitive I/O module that requires detailed control.
    • Used on microcomputers.

    I/O Instructions
    • Processor views I/O operations in a similar manner as memory operations.
    • Each device is given a unique identifier or address.
    • Processor issues commands containing device address – I/O module must check
      address lines to see if the command is for itself.

    I/O mapping

    ®   Memory-mapped I/O
    • Single address space for both memory and I/O devices (disadvantage – uses up
       valuable memory address space).
    • I/O module registers treated as memory addresses.
    • Same machine instructions used to access both memory and I/O devices
      advantage – allows for more efficient programming
    • Single read line and single write lines needed.
    • Commonly used.
    ®   Isolated I/O
    • Separate address space for both memory and I/O devices
    • Separate memory and I/O select lines needed
    • Small number of I/O instructions
    • Commonly used
    I/O techniques

    Programmed I/O
    ®   Processor executes an I/O instruction by issuing command to appropriate I/O module.
    ®   I/O module performs the requested action and then sets the appropriate bits in the I/O
          status register – I/O module takes no further action to alert the processor – it does not
          interrupt the processor.
    ®  The processor periodically checks the status of the I/O module until it determines that the
          operation is complete.

    Interrupt-Driven I/O
    ®   Overcomes the processor having to wait long periods of time for I/O modules.
    ®   The processor does not have to repeatedly check the I/O module status.
    ®   I/O module view point
    •      I/O module receives a READ command form the processor.
    •      I/O module reads data from desired peripheral into data register.
    •      I/O module interrupts the processor.
    •      I/O module waits until data is requested by the processor.
    •      I/O module places data on the data bus when requested.
    ®   Processor view point
    •      The processor checks for interrupts at the end of the instruction cycle.
    •      The processor saves the current context when interrupted
            by the I/O module.
    •      The processor read the data from the I/O module and stores it in memory.
    •      The processor the restores the saved context and resumes execution.

    Direct Memory Access (DMA)

    Drawback of Programmed and Interrupt-Driven I/O
    • I/O transfer rate limited to speed that processor can test and service devices.
    • Processor tied up managing I/O transfers.

    DMA Function
    • DMA module on system bus used to mimic the processor.
    • DMA module only uses system bus when processor does not need it.
    • DMA module may temporarily force processor to suspend operations – cycle stealing.

    DMA Operation
    • The processor issues a command to DMA module
    ®   Read or write.
    ®   I/O device address using data lines.
    ®   Starting memory address using data lines – stored in address register.
    ®  Number of words to be transferred using data lines – stored in
         data register.

    • The processor then continues with other work.
    • DMA module transfers the entire block of data – one word at a time – directly to or from
      memory without going through the processor.
    • DMA module sends an interrupt to the processor when complete.

    DMA configuration

    •      Single bus – detached DMA module.
    •      Each transfer uses bus twice – I/O to DMA, DMA to memory.
    •      Processor suspended twice.

    •      Single bus – integrated DMA module.
    •      Module may support more than one device.
    •      Each transfer uses bus once – DMA to memory.
    •      Processor suspended once.



    •      Separate I/O bus.
    •      Bus supports all DMA enabled devices.
    •      Each transfer uses bus once – DMA to memory.
                      •      Processor suspended once.

    I/O Commands



    The processor issues an address, specifying I/O module and device, and an I/O
    command. The commands are:
    ®   Control: activate a peripheral and tell it what to do.
    ®   Test: test various status conditions associated with an I/O module and its
    ®   peripherals.
    ®   Read: causes the I/O module to obtain an item of data from the peripheral and
    ®   place it into an internal register.
    ®   Write: causes the I/O module to take a unit of data from the data bus and.
    ®   transmit it to the peripheral.

    Design Issues
    How does the processor determine which device issued the interrupt.
    How are multiple interrupts dealt with?
    ®   Multiple interrupt lines – each line may have multiple I/O modules

    ®   Software poll – poll each I/O module
    •      Separate command line – TESTI/O.
    •      Processor read status register of I/O module.
    •      Time consuming.

    ®   Daisy chain
    •      Hardware poll.
    •      Common interrupt request line.
    •      Processor sends interrupt acknowledge.
    •      Requesting I/O module places a word of data on the data lines – “vector”.
    •      that uniquely identifies the I/O module – vectored interrupt.

                                          ®   Bus arbitration
                                                                      •      I/O module first gains control of the bus.
                                                                      •      I/O module sends interrupt request.
                                                                      •      The processor acknowledges the interrupt
                                                                              request.
                                                                      •      I/O module places its vector of the data lines.


    The Evolution of the I/O Function
    1.   Processor directly controls peripheral device.
    2.   Addition of a controller or I/O module – programmed I/O.
    3.   Same as 2 – interrupts added.
    4.   I/O module direct access to memory using DMA.
    5.   I/O module enhanced to become processor like – I/O channel.
    6.   I/O module has local memory of its own – computer like – I/O processor.













Pipelining & RISCs

Introduction to Pipelining

Pipelining and parallelism are 2 methods used to achieve concurrency.
·      -   Pipelining increases concurrency by dividing a computation into a number of steps.
·      -  Parallelism is the use of multiple resources to increase concurrency.

Pipelining is a key implementation technique used to build fast processors that can be seen in RISC architecture. It allows the execution of multiple instructions to overlap in time.
In a non-pipelined processing, by contrast, the next data/instruction is processed after the entire processing of the previous data/instruction is complete.



Pipelined Laundry: Start work ASAP
LESSONS:
  • Pipelining doesn’t help latency of single task, it helps throughput of entire workload
  • Multiple tasks operating simultaneously using different resources
  • Potential speedup = Number pipe stages
  • Pipeline rate limited by slowest pipeline stage
  • Unbalanced lengths of pipe stages reduces speedup
Instruction of Pipelining
Typical instruction execution sequences:
—     fetch, decode, read, execute, write, etc
In a non-pipelined CPU, instructions are performed “one at a time”.ie. before an instruction is begun, the preceding instruction is completed.
To implement instruction pipelining, desirable features of (instruction set) IS:
o   all instructions same length
o   registers specified in same place in instruction
o   memory operands only in loads or stores, i.e. RISC

Two Stage Instruction Pipeline



Pipelining of Unequal Stages
Important for pipelining where stages are unequal:
—     Always take the largest of the stage delay to be the cycle time
—     No stage overlaps and latency must be constant
—     Ensure that instruction overlap is the same as the cycle time else get timing diagram is wrong
Pipiline Performance
•         n:number of instructions
•         k: stages in pipeline
•         t : cycletime (time in seconds needed to advance a set of instructions one stage through the pipeline)
•         Tk: total time for pipelining
•         T0 : total time without pipelining
Total time for equal stages
•         For n instructions, with k equal stages and delay of t for each stage
Total time with no pipelining, T0 = nkt
Total time with pipelining, Tk = (k + (n-1))t

Speedup
•         Speedup of a k-stage pipeline for n instructions :
                                                                        S         = T0 / Tk
                                                                = nk t  / ((k+(n-1)) t
                                                                 à k (for large n)
Throughput
•         Pipelined Throughput= n/Tk (n)
•         Non-pipeline Throughput = n/To (n)
Limits to Pipelining
•         Factors that limits performance enhancement:
—    Unequal duration/delay of stages
—    Conditional branch instruction or interrupts. Ex:
–        Instruction 3 is a conditional branch to instruction 15
–        No instructions completed during time units 9-12. This is performance penalty incurred because we could not anticipate the branch
–        Flushing of pipeline
–        Pipelined operation cannot be maintained in the presence of branch or jump instructions.
Hazards as limitations to pipelining
•         3 types of hazards:
-        Resource hazards : HW cannot support this combination of instructions (single person to fold and put clothes away, washer-drier)
-        Data hazards: Instruction depends on result of prior instruction still in the pipeline
-        Data dependencies example
                                                                A = B + C
                                                                D = E + A
                                                                C = G x H
-        Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).
RISC: Reduced Instruction Set Computers
•         Major advances in computer :
—    The family concept
–        Separates architecture from implementation
—    Microprogrammed control unit
—    Cache memory
—    Solid State RAM
—    Microprocessors
—    Pipelining
–        Introduces parallelism into fetch execute cycle
—    Multiple processors
CISC and RISC
•         The next step: Reduced Instruction Set Computer in processor architecture
•         Key features of CISC:
—    Large number of predefined instructions making high level programming languages easy to design and implement.
—    Supports microprogramming to simplify computer architecture
—    Key features of RISC
—    Limited and simple instruction set
—    Large number of general purpose registers or use of compiler technology to optimize register use.
—    Emphasis on optimizing the instruction pipeline
Arguments for CISC
A rich instruction set should simplify the compiler by having instructions which match the high-level language instructions.
Since the programs are smaller in size, they have better performance



Drawbacks of CISC
-CPU complexity
-System size and cost
-Complex machine instructions may not match high-level language statements exactly, in which case they may be of little use
CISC characteristics
•         Varying number of instructions per cycle
•         Small number of general purpose registers
•         More addressing modes
•         More instruction formats : fewer instructions can be used to implement a given task
•         Use microcode
•         Variable length instruction
•         Simplified compiler: microprogram instructions could be written to match constructs of high level languages
RISC Characteristics
•         One instruction per cycle
•         Register to register operations
•         Few, simple addressing modes
•         Few, simple instruction formats
•         Hardwired design (no microcode)
•         Fixed instruction format
•         More compile time/effort

RISC vs. CISC






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